1. Field of the Invention
The present invention relates to liquid crystal display devices. More particularly it relates to liquid crystal display devices implanting in-plane switching (IPS) where an electric field to be applied to liquid crystals is generated in a plane parallel to a substrate.
2. Discussion of the Related Art
A liquid crystal display device uses the optical anisotropy and polarization properties of liquid crystal molecules to produce an image. Liquid crystal molecules have a definite orientational alignment as a result of their long, thin shapes. That orientational alignment can be controlled by an applied electric field. In other words, as an applied electric field changes, so does the alignment of the liquid crystal molecules. Due to the optical anisotropy, the refraction of incident light depends on the orientational alignment of the liquid crystal molecules. Thus, by properly controlling an applied electric field a desired light image can be produced.
Of the different types of known LCDs, active matrix LCDs (AM-LCDs), which have thin film transistors and pixel electrodes arranged in a matrix form, are the subject of significant research and development because of their high resolution and superiority in displaying moving images.
LCD devices have wide application in office automation (OA) equipment and video units because they are light and thin and have low power consumption characteristics. The typical liquid crystal display (LCD) panel has an upper substrate, a lower substrate and a liquid crystal layer interposed therebetween. The upper substrate, commonly referred to as a color filter substrate, usually includes a common electrode and color filters. The lower substrate, commonly referred to as an array substrate, includes switching elements, such as thin film transistors (TFTs) and pixel electrodes.
As previously described, LCD device operation is based on the principle that the alignment direction of the liquid crystal molecules is dependent upon an electric field applied between the common electrode and the pixel electrode. Thus, the alignment direction of the liquid crystal molecules is controlled by the application of an electric field to the liquid crystal layer. When the alignment direction of the liquid crystal molecules is properly adjusted, incident light is refracted along the alignment direction to display image data. The liquid crystal molecules function as an optical modulation element having variable optical characteristics that depend upon polarity of the applied voltage.
In a conventional LCD device, since the pixel and common electrodes are positioned on the lower and upper substrates, respectively, the electric field induced between them is perpendicular to the lower and upper substrates. However, the conventional LCD devices having the longitudinal electric field have a drawback in that they have a very narrow viewing angle. In order to solve the problem of narrow viewing angle, in-plane switching liquid crystal display (IPS-LCD) devices have been proposed. The IPS-LCD devices typically include a lower substrate where a pixel electrode and a common electrode are disposed, an upper substrate having no electrode, and a liquid crystal interposed between the upper and lower substrates. A detailed explanation about operation modes of a typical IPS-LCD panel will be provided referring to FIGS. 1, 2A, and 2B.
FIG. 1 is a schematic cross-sectional view illustrating a concept of a conventional IPS-LCD panel. As shown in FIG. 1, upper and lower substrates 10 and 20 are spaced apart from each other, and a liquid crystal layer 30 is interposed therebetween. The upper and lower substrates 10 and 20 are often referred to as an array substrate and a color filter substrate, respectively. On the lower substrate 20 are a common electrode 22 and a pixel electrode 24. The common and pixel electrodes 22 and 24 are aligned parallel to each other. On a surface of the upper substrate 10, a color filter layer (not shown) is commonly positioned between the pixel electrode 24 and the common electrode 22 of the lower substrate 20. A voltage applied across the common and pixel electrodes 22 and 24 produces an electric field 26 through the liquid crystal 32. The liquid crystal 32 has a positive dielectric anisotropy, and thus it aligns parallel to the electric field 26.
FIGS. 2A and 2B conceptually help illustrate the operation of a conventional IPS-LCD device. When no electric field is produced by the common and pixel electrodes 22 and 24, i.e., off state, as shown in FIG. 2A, the longitudinal axes of the liquid crystal (LC) molecules 32 are parallel and form a definite angle with the common and pixel electrodes 22 and 24. For example, the longitudinal axes of the LC molecules 32 are arranged parallel with both the common and pixel electrodes 22 and 24.
On the contrary, when an electric voltage is applied to the common and pixel electrodes 22 and 24, i.e., on state, as shown in FIG. 2B, because the common and pixel electrodes 22 and 24 are on the lower substrate 20, an in-plane electric field 26 that is parallel to the surface of the lower substrate 20 is produced. Accordingly, the LC molecules 32 are re-arranged to bring their longitudinal axes into coincidence with the electric field. However, the first LC molecules 32a positioned corresponding to the common and pixel electrodes 22 and 24 do not change their orientation, while the second LC molecules 32b positioned between the common and pixel electrodes 22 and 24 are arranged perpendicular to the common and pixel electrodes 22 and 24. Therefore, the result is a wide viewing angle that ranges from about 80 to 85 degrees in up-and-down and left-and-right sides from a line vertical to the IPS-LCD panel, for example.
FIG. 3 is a plan view illustrating one pixel of an array substrate according to a conventional IPS-LCD device. As shown, a gate line 66 is transversely arranged and a data line 70 is disposed substantially perpendicular to the gate line 66. A pair of gate and data lines 66 and 70 define a pixel region on the array substrate. An island-shaped semiconductor layer 84 is positioned near the crossing of the gate and data lines 66 and 70, thereby forming a thin film transistor (TFT) “T” with a gate electrode 80, a source electrode 86 and a drain electrode 88. The gate electrode 80 extends from the gate line 66, and the source electrode 86 extends from the data line 70. The drain electrode 88 is connected to a pixel connecting line 72 that connects a plurality of pixel electrodes 74 to each other. A common line 64 is spaced apart from the gate line 66 and disposed parallel with the gate line 66. A plurality of common electrodes 62 protrude from the common line 64 and are disposed parallel to each of the pixel electrodes 74, so that each common electrode 62 is spaced apart from the adjacent pixel electrodes 64 with a predetermined interval therebetween.
At the ends of the gate and data lines 66 and 70, gate and data pads 67 and 71 are respectively positioned for a connection with the external driving circuits (not shown). A gate pad electrode 75 and a data pad electrode 77 are disposed on the gate pad 67 and the data pad 71, respectively. A gate pad contact hole 83 and a data pad contact hole 73 are formed over the gate pad electrode 75 and the data pad electrode 77, respectively, to expose those electrodes for the connection with the external driving circuits.
FIGS. 4A to 4G, 5A to 5G and 6A to 6G are cross-sectional views taken along line IV-IV, V-V and VI-VI of FIG. 3, respectively illustrating process steps of manufacturing the array substrate of a conventional IPS-LCD. FIGS. 4A to 4G show the steps of forming the thin film transistor; FIGS. 5A to 5G show the steps of forming the common and pixel electrodes; and FIGS. 6A to 6G show the steps of forming the gate pad.
In FIGS. 4A, 5A and 6A, a first metal layer is deposited on a substrate 1 using sputtering and then patterned using a first mask to form a gate electrode 80, a common electrode 62, and a gate line 66 having a gate pad 67 at an end of the gate line 66. Although not shown in FIGS. 4A, 5A and 6A, the common line 64 of FIG. 3 is formed with the gate line 66. Aluminum, tungsten, tantalum, titanium or the alloy thereof is mainly used for the first metal layer.
Now referring to FIGS. 4B, 5B and 6B, after the anodically oxidized mask is formed by the direct drawing, the substrate 1 having the patterned first metal layer is immersed in an anodically oxidizing solution, e.g., a solution prepared of 3% tartaric acid with a pH value adjusted to about 6.25 with ammonia. Then, anodic oxidation is carried out to form an Al2O3 film 81 having a predetermined thickness. As illustrated in FIGS. 4B, 5B and 6B, the Al2O3 film 81 is disposed on the gate electrode 80, the common electrode 62 and the gate line 66, but the Al2O3 film 81 is not disposed on the gate pad 67 or in a pad portion “I.” In the direct drawing, the mask is directly printed on the surface of the pad portion “I.” Therefore, the Al2O3 film 81 is formed using the anodic oxidation on the surface of the patterned first metal except for the pad portion “I.”
In FIGS. 4C, 5C and 6C, a transparent conductive material, such as Indium Tin Oxide (ITO), is formed over the substrate and then patterned using a second mask to form a gate pad electrode 75. As shown in FIG. 6C, the gate pad electrode 75 is disposed in the pad portion “I” and acts to decrease contact resistance between the gate pad 67 and the external driving circuits that will be connected in a later step.
Next, as shown in FIGS. 4D, 5D and 6D, a gate insulation layer 82 is formed over the substrate 1 to cover the gate electrode 81, the common electrode 62, the gate line 66 and the gate pad 67. The gate insulation layer 82 is usually made of silicon nitride (SiNx) or silicon oxide (SiO2) and deposited on the substrate 1 using a Plasma Enhanced Chemical Vapor Deposition (PECVD). Thereafter, a pure amorphous silicon (a-Si:H) and an impurity-doped amorphous silicon (n+a-Si:H) are sequentially formed on the gate insulation layer and then simultaneously patterned to form an active layer 84a and an ohmic contact layer 84b over the gate electrode 80. The ohmic contact layer 84b drops the contact resistance between the active layer 84a and the later formed source and drain electrodes.
Referring to FIGS. 4E, 5E and 6E, a portion of the gate insulation layer 82 is etched using a fourth mask to form a first gate pad contact hole 83a. The first gate pad contact hole 83a exposes a portion of the gate pad electrode 75 and connects the gate pad 67 to the external driving circuits therethrough.
In FIGS. 4F, 5F and 6F, a second metal layer and a third metal layer are sequentially formed on the gate insulation layer 82 and then patterned using a fifth mask to form a source electrode 86, a drain electrode 88 and a pixel electrode 74. At this time, the data line 70, data pad 71 and pixel connecting line 72 of FIG. 3 are also formed with the source and drain electrodes 86 and 88. The second metal layer is a material selected from chromium (Cr), molybdenum (Mo), tungsten (W) and the like. The third metal layer is formed of a material selected from aluminum, tungsten, tantalum, palladium and an alloy thereof.
A portion of the ohmic contact layer 84b disposed on the active layer 84a is etched using the source and drain electrodes 86 and 88 as masks, thereby forming a channel “CH” in an interval between the source electrode 86 and the drain electrodes 88 as shown in FIG. 4F. Accordingly, the thin film transistor “T” including the gate electrode 80, the semiconductor layer 84 and the source and drain electrodes 86 and 88 is complete.
Referring to FIGS. 3 and 5F, since the data line 70 and the pixel electrode 74 are disposed in the same plane, the pixel electrode 74 should be formed in an inner part of the pixel region rather than the common electrode 62. This is to prevent the electrical interference between the data line 70 and the pixel electrode 74.
In FIGS. 4G, 5G and 6G, a passivation layer 90 that protects the thin film transistor “T” is formed on the whole surface of the substrate 1 to cover the thin film transistor “T” and a pixel electrode 74. The passivation layer 90 is silicon nitride (SiNx) or silicon oxide (SiO2) and it is thicker than the gate insulation layer 82. Thereafter, a portion of the passivation layer 90 is etched using a sixth mask to form a second gate pad contact hole 83b that corresponds to the first gate pad contact hole 83a of FIG. 6E.
As mentioned hereinbefore, the array substrate for use in the conventional IPS-LCD is fabricated though the six mask processes. Among these processes, the process for forming the gate pad electrode and the data pad electrode using a transparent conductive material can be omitted because of reducing the cost of production. Furthermore, the first and second gate and data pad contact holes can simultaneously be formed in the same mask process. Therefore, the array substrate for the conventional IPS-LCD can be formed through four mask processes.
After completing the above-mentioned processes, an annealing process is followed to improve the property of the thin film transistor. Through the process of annealing, the implanted impurity ions can be diffused and activated, and the problem of internal grain defects and the internal stress are removed. Thus, the annealing process improves the electrical properties of the thin film transistor.
After the process of annealing, electrical testing of the gate and data lines and the thin film transistor is performed to ensure the stability of them. Namely, through the electrical tests, the open/short-circuit of the gate and data lines are detected and the operation of the thin film transistor is observed.
The array substrate fabricated by above-processes is then aligned with and attached to the upper substrate with the liquid crystal layer interposed therebetween, i.e., a cell process. However, before attaching the upper substrate to the array substrate and interposing the liquid crystal layer between the upper substrate and the array substrate, alignment layers that align the liquid crystal molecules in a determined direction are formed on the array substrate and the upper substrate. Namely, the cell process includes forming the alignment layer in a preliminary step thereof.
When forming the alignment layer, a polymeric material is applied to the substrate and then cured at a temperature of predetermined condition. Thereafter, the alignment layer is rubbed in a certain direction to orient the liquid crystal molecules.
The heat treatment process of curing the alignment layer is generally executed under the condition of annealing the thin film transistor. Namely, the heat treatment process has the same process condition as the annealing process. However, since these processes are carried out at different times in the array process and the cell process, there are problems of increasing the production cost and time.